Hardware/Software Codesign for Real-Time Digital Systems with an Emphasis on Applications to Robotics
Dr. Vincent J. Mooney IIIProfessor, School of ECE, Georgia Tech
Date: Wednesday, April 9, 2008 at 12:00 PM
Room: ELAB 38
Abstract
An indispensable component to a system consisting of cooperating hardware and software is a run-time scheduler. I will explain an approach to run-time scheduler synthesis to support course-grained hardware-software partitioning, where a system consists of tasks implemented as Hardware Description Language (HDL) modules or software threads. Thus, given an already partitioned input system specification in C and Verilog HDL, a run-time scheduler partly in hardware and partly in software is generated. The Computer Aided Design (CAD) tool, called the Serra Synthesis System, builds on available microprocessor cores and hardware synthesis tools. I will explain the target architecture, tool flow and real-time analysis of Serra. A sample implementation of the run-time scheduler in an actual design, a force-feedback haptic robot, will be described. In the real-time robotics application, the hardware part of the scheduler was implemented on a Xilinx FPGA communicating with software using the PCI protocol. (Note: this implementation was carried out at Stanford University, where the author completed his Ph.D. in June of 1998.) In addition, a brief overview will be given of projects in low power and real-time systems carried out by the Hardware/Software Codesign Group at Georgia Tech.
Presenter Bio
Vincent J. Mooney III (Senior Member, IEEE and Member, ACM) received the B.S. degree from Yale University in 1991, where he double majored in Electrical Engineering and Computer Science. He was a member of the 1989 Ivy League Championship football team for Yale and was one of 29 football players to be awarded the NCAA Postgraduate Scholarship upon his graduation in 1991. During the '91 - '92 school year he did research on real-time vision systems at the "Centro de Estudios e Investigaciones Tecnicas" (CEIT) in San Sebastian, Spain. CEIT is affiliated with the School of Engineering of the University of Navarra. He received an M.S. degree in E.E. from Stanford University in 1994, an M.A. degree in Philosophy from Stanford in 1997, and the Ph.D. degree in E.E. from Stanford in June of 1998. He has worked at Bell Labs (Lucent), Allied Signal Aerospace VLSI Design Group, Hughes Network Systems, and Redwood Design Automation (acquired by Cadence). He is currently an Associate Professor in the School of Electrical and Computer Engineering and an Adjunct Associate Professor in the College of Computing, both at the Georgia Institute of Technology in Atlanta, GA. He is a recipient of the NSF Career Award. He is Co-Director of the Advanced Center for Embedded Systems (ACES) at Georgia Tech. He was General Chair of IFIP VLSI-SoC 2007. He is an Associate Editor of both the IEEE Transactions on VLSI as well as the ACM Transactions on Embedded Computing Systems. His research interests include computer-aided design of integrated circuits with a particular emphasis on hardware-software codesign, reconfigurable computing, real-time operating systems and power-aware architectures, compilers and circuits.
